Our greatest challenge during the initial stages of development was controlling processing precision. Any loss of processing precision will cause color and sensitivity variations in a CMOS sensor. If you increase the size of a CMOS sensor, you also increase the risk of horizontal and vertical imperfections, and it becomes proportionately more difficult to maintain the necessary processing precision. However, some aspects of optical characteristics, such as color variations, do not become apparent until you actually produce a sensor. So we had to go through repeated cycles of simulation checking and prototype creation until we developed a sensor supporting the kind of imaging quality we were seeking.
Yield was a major issue at the manufacturing stage. The dominant factor influencing yield was the presence of sub-micron particles. Although the clean room in the manufacturing plant provides extremely advanced dust protection, the density of the imaging elements and the circuits and wiring around them is so high, that a single particle falling onto a sensor can short out the circuitry and render the element useless. We tend to think of particles as things that float around in the air, but in fact they can appear in unexpected places. For example, particles are sometimes produced when materials are transported.
We decided to design circuits that would be less vulnerable to particles. This approach was based on a concept known as "design for manufacturing" (DFM). DFM is a circuit design technology that takes into account problems arising from manufacturing technology. We devised an element and wiring layout for a full-sized CMOS sensor that allowed us to reduce vulnerability to particles from the design stage. A lot of effort went into production line improvements. For example, we installed production equipment made from materials that were less likely to produce particles. These measures brought about gradual improvements in yields.
During APS-C size sensor development, we also carried out manufacturing simulations for a full-size CMOS sensor, and we had a general idea of what to expect because of our work on pixel design, specification development and other aspects. However, when we took photographs with the prototype sensor, we noticed a problem. Noise that was imperceptible with an APC-C sensor was significantly expanded and became much more obvious.
A full-size CMOS sensor has a larger photosensitive area than an APS-C CMOS sensor, and care must be taken to ensure compatibility between the area around the field and the optical system. Light traveling through the center lens reaches the CMOS sensor in a roughly vertical direction. However, light that passes through peripheral areas of the lens follows a slanting path to the lens. This results in reduced sensitivity, color variation and other phenomena. To solve this problem, we reduced the distance to the photodiodes to ensure that peripheral light would also reach the image sensor, and we also improved the overall flatness of the chip. In a full-size chip, even minute differences in light wavelengths can cause major color variations, so enhancing flatness has remained an important priority.
This process required exquisite artisanship. The slightest change to the processing conditions would radically alter the characteristics of the chip. When the conditions were right, however, the chip seemed to respond to our efforts. It was as if we were working with a living thing.
Our goal was not to achieve optimal characteristics on a pinpoint basis, but rather to achieve the same characteristics consistently. This was extremely important from a manufacturing perspective. Our efforts to meet this requirement would result not only in manufacturing parameter adjustments, but also in major modifications to the entire manufacturing process.
No comments:
Post a Comment